Intel highlights the most recent architectural and packaging innovations that enable 2.5D and 3D tile-based chip designs at Hot Chips 34, ushering in a new era in chipmaking and propelling Moore’s Law forward for years to come.
Intel CEO Pat Gelsinger shared the company’s path for continuing its pursuit of more powerful compute, providing details from across the company’s upcoming portfolio.
“Combined with other advances like RibbonFET, PowerVia, High NA lithography and developments with 2.5D and 3D packaging, we have an aspiration to move from 100 billion transistors on a package today to 1 trillion by 2030. There has never been a better — to be a technologist. We must all be ambassadors for the crucial role semiconductors play in life today,” Gelsinger said.
In a statement, Intel stated the industry is entering a new golden age of semiconductors, an era in chipmaking which requires a shift from the traditional foundry model mindset to a systems foundry. According to the company, Intel’s systems foundry model integrates advanced packaging, an open chiplet ecosystem, and software components to assemble and deliver systems in a package that meets the world’s demand for compute power and fully immersive digital experiences. Intel said the company is also addressing industry demand by continuing to advance process technology and tile-based design.
Intel also previewed product architectures from next-generation technologies such as Meteor Lake processor, Arrow Lake processor, Lunar Lake processor, Ponte Vecchio, Xeon D-2700 and 1700 series, and FPGA technology.
According to Intel, Meteor Lake, Arrow Lake, and Lunar Lake processors will revolutionise personal computers with tile-based chip designs that increase manufacturing, power, and performance efficiencies. It is accomplished by stacking discrete CPU, GPU, SoC, and I/O tiles in 3D configurations using Intel’s Foveros interconnect technology. Intel said the platform transformation is bolstered by industry support for the open Universal Chiplet Interconnect Express (UCleTM) specification, which allows chiplet designed and manufactured on different technologies by different vendors to work together when integrated with advanced packaging technologies.
The Intel Data Center GPU, code-named Ponte Vecchio, was built to address compute density across high-performance computing (HPC) and AI supercomputing workloads. According to Intel, it fully utilises Intel’s open software model, using OneAPI to simplify API abstractions and cross-architecture programming. Ponte Vecchio is made up of several complex designs that manifest in tiles, linked together by a combination of embedded multi-die interconnect bridge (EMIB) and Foveros advanced packaging technologies. Intel said the high-speed MDFI interconnect enables the package to scale up to two stacks, allowing a single package to contain over 10 billion transistors.
According to Intel, the Xeon D-2700 and 1700 series are designed to address edge use cases for 5G, IoT, enterprise, and cloud applications, with particular consideration to the power and space constraints typical in many real-world implementations. Intel stated that it features cutting-edge compute cores, 100G Ethernet with flexible packet processor, inline crypto acceleration, time coordinated computing (TCC), time-sensitive networking (TSN), and built-in optimisation for AI processes.
Meanwhile, Intel said the FPGA technology remains a powerful and flexible tool for hardware acceleration, with particular promise for radio frequency (RF) applications. Intel has discovered new efficiencies by combining digital and analogue chiplets and chiplets from different process nodes and foundries, reducing development time and maximising flexibility for developers.
